Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions, and may function to interface with other integrated circuits or components of electronic devices. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, processors, clock managers, delay lock loops (DLLs), etc.
The programmable logic of a programmable logic device implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, etc. The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA. Another common programmable logic device is a complex programmable logic device (CPLD). For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
An On-Chip Memory (OCM) controller, which is also typically provided on an FPGA having a processor, serves as a dedicated interface between the BRAMs in the FPGA and OCM signals available on an embedded processor, such as a PowerPC™ processor available from IBM Corporation. The OCM signals are designed to provide quick access to a fixed amount of instruction and data memory space. The OCM controller, which typically comprises an instruction side on-chip memory (ISOCM) controller and a data side on-chip memory (DSOCM) controller, provides an interface to both an Instruction-Side Block RAM (ISBRAM) and a Data-Side Block RAM (DSBRAM). A designer of an FPGA can choose to implement any combination of ISBRAM and/or DSBRAM. A typical application for a DSOCM controller includes enabling a dual-port feature of BRAM to provide bi-directional data transfers between a processor and circuits of an FPGA.
However, such conventional DSOCM controllers have a fixed latency of operation. That is, data is read from or written to a memory of the FPGA in a fixed number of BRAM clock cycles. A fixed latency approach guarantees that the data load and data store operations are completed in a predetermined, fixed number of BRAM clock cycles. This guarantees a deterministic performance between the DSOCM controller and on-chip BRAMs of an FPGA, for example. FIG. 1 comprises a conventional circuit for reading data from or writing data to a memory. As shown in FIG. 1, address information, control signals, and data to be written to a BRAM are provided to the BRAM in one BRAM clock cycle, while data read from the BRAM is returned in one BRAM clock cycle. Accordingly, a read operation for a BRAM employing a conventional DSOCM controller will require a predetermined number of clock cycles, namely two BRAM clock cycles.
In addition to controlling a BRAM, the DSOCM controller may also interface with other peripheral devices, including for example hardware circuits of the FPGA or external RAM. Depending upon the devices being controlled by the DSOCM controller, data may be sent to a device from the DSOCM controller or received by the DSOCM controller at different rates. However, because conventional DSOCM controllers only provide a fixed latency operation, these conventional DSOCM controllers will operate on a predetermined number of clock cycles which is dependent upon the slowest peripheral or operation being controlled by the DSOCM controller.
Accordingly, there is a need for a method of and circuit for enabling variable latency data transfers in electronic circuits, such as programmable logic devices, which allow different peripherals and on-chip memory to run at different speeds when they are attached to a DSOCM controller.